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INTEGRATED CIRCUITS
DATA SHEET
UDA1351TS 96 kHz IEC 958 audio DAC
Preliminary specification File under Integrated Circuits, IC01 2000 Mar 28
Philips Semiconductors
Preliminary specification
96 kHz IEC 958 audio DAC
CONTENTS 1 1.1 1.2 1.3 1.4 2 3 4 5 6 7 8 8.1 8.2 8.3 8.4 8.4.1 8.4.2 8.4.3 8.4.4 8.4.5 8.5 8.5.1 8.5.2 8.6 8.6.1 8.6.2 8.6.3 8.6.4 8.6.5 8.6.6 8.6.7 8.6.8 8.6.9 FEATURES General Control IEC 958 input Digital sound processing and DAC APPLICATIONS GENERAL DESCRIPTION QUICK REFERENCE DATA ORDERING INFORMATION BLOCK DIAGRAM PINNING FUNCTIONAL DESCRIPTION Clock regeneration and lock detection Mute Auto mute Data path IEC 958 input Audio feature processor Interpolator Noise shaper The Filter Stream DAC (FSDAC) Control Static pin control mode L3 control mode L3 interface General Device addressing Register addressing Data write mode Data read mode initialization string Overview of L3 interface registers Writable registers Readable registers 16 17 15.2 15.3 15.4 15.5 9 10 11 12 13 14 15 15.1 LIMITING VALUES
UDA1351TS
THERMAL CHARACTERISTICS CHARACTERISTICS TIMING CHARACTERISTICS APPLICATION INFORMATION PACKAGE OUTLINE SOLDERING Introduction to soldering surface mount packages Reflow soldering Wave soldering Manual soldering Suitability of surface mount IC packages for wave and reflow soldering methods DEFINITIONS LIFE SUPPORT APPLICATIONS
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Philips Semiconductors
Preliminary specification
96 kHz IEC 958 audio DAC
1 1.1 FEATURES General
UDA1351TS
* 2.7 to 3.6 V power supply * Integrated digital filter and Digital-to-Analog Converter (DAC) * Master-mode data output and input interface for off-chip sound processing * 256fs system clock output * 20-bit data path in interpolator * High performance * No analog post filtering required for DAC * Support sampling frequencies from 28 kHz up to 100 kHz * The UDA1351TS is fully pin and function compatible with the UDA1350ATS. 1.2 Control 3 GENERAL DESCRIPTION Available in two versions: * UDA1351TS: - only IEC 958 input to DAC in SSOP28 package. * UDA1351H: - full featured version in QFP44 package. The UDA1351TS is a single chip IEC 958 audio decoder with an integrated stereo DAC employing bitstream conversion techniques. A lock indication signal is available on pin LOCK, indicating that the IEC 958 decoder is locked. This pin is also used to indicate whether PCM data is applied to the input or not. When non-PCM data is detected, the device indicates out-of-lock. By default, the DAC output and the data output interface are muted when the decoder is out-of-lock. However, this setting can be overruled in the L3 control mode. Controlled either by means of static pins or via the L3 microcontroller interface. 1.3 IEC 958 input 2 APPLICATIONS Digital audio systems.
* On-chip amplifier for converting IEC 958 input to CMOS levels * Lock indication signal available on pin LOCK * Lock indication signal combined on-chip with the Pulse Code Modulation (PCM) status bit; when non-PCM is detected, pin LOCK indicates out-of-lock * Key channel-status bits available via L3 interface (lock, pre-emphasis, audio sample frequency, two channel PCM indication and clock accuracy). 1.4 Digital sound processing and DAC
* Automatic de-emphasis when using IEC 958 input with 32.0, 44.1 and 48.0 kHz audio sample frequencies * Soft mute by means of a cosine roll-off circuit selectable via pin MUTE or the L3 interface * dB linear volume control with 1 dB steps from 0 dB to -60 dB and - dB * Bass boost and treble control in L3 control mode * Interpolating filter (fs to 128fs) by means of a cascade of a recursive filter and a FIR filter * Third order noise shaper operating at 128fs generates the bitstream for the DAC * Filter Stream DAC (FSDAC).
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Philips Semiconductors
Preliminary specification
96 kHz IEC 958 audio DAC
4 QUICK REFERENCE DATA SYMBOL Supplies VDDD VDDA IDDA(DAC) IDDA(PLL) IDDD(C) IDDD P digital supply voltage analog supply voltage analog supply current of DAC analog supply current of PLL digital supply current of core digital supply current power-on power-down at 48 kHz at 96 kHz at 48 kHz at 96 kHz at 48 kHz at 96 kHz power consumption at 48 kHz DAC in playback mode DAC in Power-down mode power consumption at 96 kHz DAC in playback mode DAC in Power-down mode General trst Tamb Vo(rms) reset active time ambient temperature - -40 note 1 fi = 1.0 kHz tone at 48 kHz at 0 dB at -40 dB; A-weighted fi = 1.0 kHz tone at 96 kHz at 0 dB at -40 dB; A-weighted S/N cs Vo Note 1. The output voltage of the DAC is proportional to the DAC power supply voltage. 5 ORDERING INFORMATION TYPE NUMBER UDA1351TS PACKAGE NAME SSOP28 DESCRIPTION plastic shrink small outline package; 28 leads; body width 5.3 mm - - - - - 2.7 2.7 - - - - - - - - - - - - PARAMETER CONDITIONS MIN.
UDA1351TS
TYP.
MAX.
UNIT
3.0 3.0 8.0 750 0.7 1.0 16.0 24.5 2.0 3.0 80 58 109 87
3.6 3.6 - - - - - - - - - - - - - +85 - -85 -55 -80 -52 - - - 0.4
V V mA A mA mA mA mA mA mA mW mW mW mW s C mV dB dB dB dB dB dB dB dB
250 - 900 -90 -60 -85 -57 100 100 96 0.1
Digital-to-analog converter output voltage (RMS value) (THD + N)/S total harmonic distortion-plus-noise to signal ratio
signal-to-noise ratio at 48 kHz fi = 1.0 kHz tone; code = 0; A-weighted 95 signal-to-noise ratio at 96 kHz fi = 1.0 kHz tone; code = 0; A-weighted 95 channel separation unbalance of output voltages fi = 1.0 kHz tone fi = 1.0 kHz tone - -
VERSION SOT341-1
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Philips Semiconductors
Preliminary specification
96 kHz IEC 958 audio DAC
6 BLOCK DIAGRAM
UDA1351TS
handbook, full pagewidth
TEST1
TEST3 TEST4 28 25
VSSA VDDA 21 22
VDDA(DAC) VOUTL 15
Vref VOUTR 19 17
TEST2 4 18
VSSA(DAC) 14 20
VDDA(PLL) VSSA(PLL)
24 23
CLOCK AND TIMING CIRCUIT
DAC
DAC
NOISE SHAPER VDDD(C) 6
UDA1351TS
INTERPOLATOR
L3MODE L3CLOCK L3DATA SELSTATIC
10 9 8 26 SLICER L3 INTERFACE AUDIO FEATURE PROCESSOR 11 MUTE
SPDIF VDDD VSSD VSSD(C)
13 3 7 12 1, 2, 27 n.c.
IEC 958 DECODER
5
RESET
16
MGU032
LOCK
Fig.1 Block diagram.
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Philips Semiconductors
Preliminary specification
96 kHz IEC 958 audio DAC
7 PINNING SYMBOL n.c. n.c. VDDD TEST1 RESET VDDD(C) VSSD L3DATA L3CLOCK L3MODE MUTE VSSD(C) SPDIF VDDA(DAC) VOUTL LOCK VOUTR TEST2 Vref VSSA(DAC) VSSA VDDA VSSA(PLL) VDDA(PLL) TEST4 SELSTATIC n.c. TEST3 Note 1. See Table 1. PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 - - DS DID DISD DS DGND DIOS DIS DIS DID DGND AI AS AO DO AO DID A AGND AGND AS AGND AS DIU DIU - DISD TYPE(1) not connected not connected digital supply voltage DESCRIPTION
UDA1351TS
test pin 1; must be connected to digital ground (VSSD) reset input digital supply voltage for core digital ground L3 interface data input and output L3 interface clock input L3 interface mode input mute control input digital ground IEC 958 channel input analog supply voltage for DAC analog DAC left channel output SPDIF and PLL lock indicator output analog DAC right channel output test pin 2; must be connected to digital ground (VSSD) DAC reference voltage analog ground for DAC analog ground analog supply voltage analog ground for PLL analog supply voltage for PLL test pin 4; must be connected to the digital supply voltage (VDDD) static pin control selection input not connected test pin 3; must be connected to digital ground (VSSD)
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Philips Semiconductors
Preliminary specification
96 kHz IEC 958 audio DAC
Table 1 Pin type references DESCRIPTION digital supply digital ground analog supply analog ground digital input digital Schmitt-triggered input digital input with internal pull-down resistor digital Schmitt-triggered input with internal pull-down resistor digital input with internal pull-up resistor digital output digital input and output digital Schmitt-triggered input and output analog reference voltage analog input analog output
UDA1351TS
PIN TYPE DS DGND AS AGND DI DIS DID DISD DIU DO DIO DIOS A AI AO
handbook, halfpage
n.c. n.c. VDDD TEST1 RESET VDDD(C) VSSD L3DATA L3CLOCK
1 2 3 4 5 6 7
28 TEST3 27 n.c. 26 SELSTATIC 25 TEST4 24 VDDA(PLL) 23 VSSA(PLL)
UDA1351TS
8 9
22 VDDA 21 VSSA 20 VSSA(DAC) 19 Vref 18 TEST2 17 VOUTR 16 LOCK 15 VOUTL
L3MODE 10 MUTE 11 VSSD(C) 12 SPDIF 13 VDDA(DAC) 14
MGU033
Fig.2 Pin configuration.
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Philips Semiconductors
Preliminary specification
96 kHz IEC 958 audio DAC
8 FUNCTIONAL DESCRIPTION
1
UDA1351TS
The UDA1351TS is a low cost audio IEC 958 decoder with an on-board DAC. The minimum audio input sampling frequency conforming to the IEC958 standard is 28.0 kHz and the maximum audio sampling frequency is 100.0 kHz. 8.1 Clock regeneration and lock detection
MGU119
handbook, halfpage
mute factor 0.8
The UDA1351TS contains an on-board PLL for regenerating a system clock from the IEC 958 input bitstream. Note: If there is no input signal, the PLL generates a minimum frequency and the output spectrum shifts accordingly. Since the analog output does not have an analog mute, this means noise that is out of band under normal conditions can move into the audio band. When the on-board clock locks to the incoming frequency, the lock indicator bit is set and can be read via the L3 interface. Internally, the PLL lock indication is combined with the PCM status bit of the input data stream. When both the IEC 958 decoder and the on-board clock have locked to the incoming signal and the input data stream is PCM data, pin LOCK will be asserted. However, when the IC is locked but the PCM status bit reports non-PCM data, pin LOCK is returned to LOW level. The lock indication output can be used, for example, for muting purposes. The lock signal can be used to drive an external analog muting circuit to prevent out of band noise from becoming audible when the PLL runs at its minimum frequency (e.g. when there is no SPDIF input signal). 8.2 Mute
0.6
0.4
0.2
0 0 5 10 15 20 t (ms) 25
Fig.3 Mute as a function of raised cosine roll-off.
8.3
Auto mute
By default, the DAC outputs will be muted until the IC is locked, regardless of the level on pin MUTE (in static mode) or the state of bit MT of the sound feature register (in L3 mode). In this way, only valid data will be passed to the outputs. This mute is done in the SPDIF interface and is a hard mute, not a cosine roll-off mute. If needed, this muting can be bypassed by setting bit AutoMT to logic 0 via the L3 interface. As a result, the IC will no longer mute during out-of-lock situations. 8.4 Data path
The UDA1351TS is equipped with a cosine roll-off mute in the DSP data path of the DAC part. Muting the DAC, by pin MUTE (in static mode) or via bit MT (in L3 mode), will result in a soft mute, as shown in Fig.3. The cosine roll-off soft mute takes 32 x 32 samples = 24 ms at 44.1 kHz sampling frequency. When operating in the L3 control mode, the device will mute on start-up. In L3 mode, it is necessary to explicitly switch off the mute for audio output by means of the MT bit in the L3 register. In the L3 mode, pin MUTE does not have any function (the same holds for several other pins) and can either be left open circuit (since it has an internal pull-down resistor) or be connected to ground.
The UDA1351TS data path consists of the IEC 958 decoder, the audio feature processor, digital interpolator and noise shaper and the DACs. 8.4.1 IEC 958 INPUT
The UDA1351TS IEC 958 decoder features an on-chip amplifier with hysteresis, which amplifies the IEC 958 input signal to CMOS level (see Fig.4). All 24 bits of data for left and right are extracted from the input bitstream as well as several of the IEC 958 key channel-status bits.
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Philips Semiconductors
Preliminary specification
96 kHz IEC 958 audio DAC
UDA1351TS
When used in the L3 control mode, it provides the following additional features: * Volume control, using 6 bits * Bass boost control, using 4 bits
handbook, halfpage
* Treble control, using 2 bits
10 nF SPDIF 13
* Mode selection of the sound processing bass boost and treble filters: flat, minimum and maximum * Soft mute control with raised cosine roll-off * De-emphasis selection of the incoming data stream for fs = 32.0, 44.1 and 48.0 kHz.
MGU034
75
180 pF
UDA1351TS
8.4.3
INTERPOLATOR
The UDA1351TS includes an on-board interpolating filter which converts the incoming data stream from 1fs to 128fs by cascading a recursive filter and a FIR filter. Fig.4 IEC 958 input circuit and typical application. Table 2 Interpolator characteristics CONDITIONS 0 to 0.45fs >0.65fs 0 to 0.45fs - NOISE SHAPER VALUE (dB) 0.03 -50 115 -3.5 PARAMETER The extracted key parameters are: * Pre-emphasis * Audio sample frequency * Two-channel PCM indicator * Clock accuracy. Both the lock indicator and the key channel status bits are accessible via the L3 interface. The UDA1351TS supports the following sample frequencies and data bit rates: fs = 32.0 kHz, resulting in a data rate of 2.048 Mbits/s fs = 44.1 kHz, resulting in a data rate of 2.8224 Mbits/s fs = 48.0 kHz, resulting in a data rate of 3.072 Mbits/s fs = 64.0 kHz, resulting in a data rate of 4.096 Mbits/s fs = 88.2 kHz, resulting in a data rate of 5.6448 Mbits/s fs = 96.0 kHz, resulting in a data rate of 6.144 Mbits/s. The UDA1351TS supports timing levels I, II and III, as specified by the IEC 958 standard. 8.4.2 AUDIO FEATURE PROCESSOR 8.4.4 The third-order noise shaper operates at 128fs. It shifts in-band quantization noise to frequencies well above the audio band. This noise shaping technique enables high signal-to-noise ratios to be achieved. The noise shaper output is converted to an analog signal using a filter stream DAC. 8.4.5 THE FILTER STREAM DAC (FSDAC) Pass-band ripple Stop band Dynamic range DC gain
The audio feature processor automatically provides de-emphasis for the IEC 958 data stream in the static pin control mode and default mute at start-up in the L3 control mode.
The FSDAC is a semi-digital reconstruction filter that converts the 1-bit data stream of the noise shaper to an analog output voltage. The filter coefficients are implemented as current sources and are summed at virtual ground of the output operational amplifier. In this way, very high signal-to-noise performance and low clock jitter sensitivity is achieved. A post-filter is not needed due to the inherent filter function of the DAC. On-board amplifiers convert the FSDAC output current to an output voltage signal capable of driving a line output. The output voltage of the FSDAC is scaled proportionally with the power supply voltage.
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Philips Semiconductors
Preliminary specification
96 kHz IEC 958 audio DAC
8.5 Control
UDA1351TS
control mode, pins L3MODE and L3DATA are used to select the format for the data output and input interface. 8.5.1 STATIC PIN CONTROL MODE
The UDA1351TS can be controlled by means of static pins or via the L3 interface. For optimum use of the features of the UDA1351TS, the L3 control mode is recommended since only basic functions are available in the static pin control mode. It should be noted that the static pin control mode and L3 control mode are mutually exclusive. In the static pin Table 3 PIN Pin description of static pin control mode NAME VALUE
The default values for all non-pin controlled settings are identical to the default values at start-up in the L3 control mode.
FUNCTION
Mode selection pin 26 Input pins 5 8 9 10 11 Status pin 16 LOCK 0 1 Test pins 4 18 25 28 TEST1 TEST2 TEST4 TEST3 0 0 1 0 must be connected to digital ground (VSSD) must be connected to digital ground (VSSD) must be connected to digital supply voltage (VDDD) must be connected to digital ground (VSSD) clock regeneration and IEC 958 decoder out-of-lock or non-PCM data detected clock regeneration and IEC 958 decoder locked and PCM data detected RESET L3DATA L3CLOCK L3MODE MUTE 0 1 0 0 0 0 1 normal operation reset must be connected to VSSD must be connected to VSSD must be connected to VSSD normal operation mute active SELSTATIC 1 select static pin control mode; must be connected to VDDD
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Philips Semiconductors
Preliminary specification
96 kHz IEC 958 audio DAC
8.5.2 L3 CONTROL MODE
UDA1351TS
The L3 control mode allows maximum flexibility in controlling the UDA1351TS. It should be noted that, in the L3 control mode, several base-line functions are still controlled by pins on the device and that, on start-up in the L3 control mode, the output is explicitly muted by bit MT via the L3 interface. Table 4 PIN Pin description in the L3 control mode NAME VALUE FUNCTION
Mode selection pin 26 Input pins 5 8 9 10 Status pin 16 LOCK 0 1 Test pins 4 18 25 28 TEST1 TEST2 TEST4 TEST3 0 0 1 0 must be connected to ground (VSSD) must be connected to ground (VSSD) must be connected to digital supply voltage (VDDD) must be connected to ground (VSSD) clock regeneration and IEC 958 decoder out-of-lock or non-PCM data detected clock regeneration and IEC 958 decoder locked and PCM data detected RESET L3DATA L3CLOCK L3MODE 0 1 - - - normal operation reset must be connected to the L3-bus must be connected to the L3-bus must be connected to the L3-bus SELSTATIC 0 select L3 control mode; must be connected to VSSD
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Philips Semiconductors
Preliminary specification
96 kHz IEC 958 audio DAC
8.6 8.6.1 L3 interface GENERAL
UDA1351TS
Basically, two types of data transfers can be defined: * Write action: data transfer to the device * Read action: data transfer from the device. Remark: when the device is powered up, at least one L3CLOCK pulse must be given to the L3 interface to wake up the interface before starting sending to the device, see Fig.5. This is only needed once after the device is powered up. 8.6.2 DEVICE ADDRESSING
The UDA1351TS has an L3 microcontroller interface and all the digital sound processing features and various system settings can be controlled by a microcontroller. The controllable settings are: * Restoring L3 defaults * Power-on * Selection of filter mode and settings of treble and bass boost * Volume settings * Selection of soft mute via cosine roll-off and bypass of auto mute * Selection of de-emphasis (only effective in L3 control mode). The readable settings are: * Mute status of interpolator * PLL locked * SPDIF input signal locked * Audio Sample Frequency (ASF) * Valid PCM data detected * Pre-emphasis of the IEC 958 input signal * ACcuracy of the Clock (ACC). The exchange of data and control information between the microcontroller and the UDA1351TS is LSB first and is accomplished through a serial hardware L3 interface comprising the following pins: * L3DATA: data line * L3MODE: mode line * L3CLK: clock line. The exchange of bytes via the L3 interface is LSB first. The L3 format has two modes of operation: * Address mode * Data transfer mode. The address mode is used to select a device for a subsequent data transfer. The address mode is characterized by L3MODE being LOW and a burst of 8 pulses on L3CLOCK, accompanied by eight bits (see Fig.5). The data transfer mode is characterized by L3MODE being HIGH and is used to transfer one or more bytes representing a register address, instruction or data.
The device address consists of one byte with: * Data Operating Mode (DOM) bits 0 and 1 representing the type of data transfer (see Table 5) * Address bits 2 to 7 representing a 6-bit device address. Table 5 Selection of data transfer DOM TRANSFER BIT 0 0 1 0 1 8.6.3 BIT 1 0 0 1 1 not used not used write data or prepare read read data
REGISTER ADDRESSING
After sending the device address (including DOM bits), indicating whether the information is to be read or written, one data byte is sent using bit 0 to indicate whether the information will be read or written and bits 1 to 7 for the destination register address. Basically, there are three methods for register addressing: 1. Addressing for write data: bit 0 is logic 0 indicating a write action to the destination register, followed by bits 1 to 7 indicating the register address (see Fig.5) 2. Addressing for prepare read: bit 0 is logic 1, indicating that data will be read from the register (see Fig.6) 3. Addressing for data read action. Here, the device returns a register address prior to sending data from that register. When bit 0 is logic 0, the register address is valid; when bit 0 is logic 1, the register address is invalid.
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L3 wake-up pulse after power-up L3CLOCK L3MODE device address L3DATA 0 1 0
MGS753
Philips Semiconductors
96 kHz IEC 958 audio DAC
register address
data byte 1
data byte 2
DOM bits
write
Fig.5 Data write mode (for L3 version 2). 13
L3CLOCK L3MODE device address L3DATA 01 DOM bits 1 read prepare read register address 11 device address 0/1 register address data byte 1 data byte 2
Preliminary specification
valid/non-valid send by the device
MGS754
UDA1351TS
Fig.6 Data read mode.
Philips Semiconductors
Preliminary specification
96 kHz IEC 958 audio DAC
8.6.4 DATA WRITE MODE
UDA1351TS
For reading data from a device, the following six bytes are involved (see Table 7): 1. One byte with the device address, including `01' for signalling the write action to the device 2. One byte is sent with the register address from which data needs to be read. This byte starts with a `1', which indicates that there will be a read action from the register, followed again by seven bits for the destination address in binary format, with A6 being the MSB and A0 being the LSB 3. One byte with the device address, including `11' is sent to the device. The `11' indicates that the device must write data to the microcontroller 4. One byte, sent by the device to the bus, with the (requested) register address and a flag bit indicating whether the requested register was valid (bit is logic 0) or invalid (bit is logic 1) 5. Two bytes, sent by the device to the bus, with the data information in binary format, with D15 being the MSB and D0 being the LSB.
The data write mode is explained in the signal diagram of Fig.5. For writing data to a device, four bytes must be sent (see Table 6): 1. One byte starting with `01' for signalling the write action to the device, followed by the device address (`011000' for the UDA1351TS) 2. One byte starting with a `0' for signalling the write action, followed by seven bits indicating the destination address in binary format with A6 being the MSB and A0 being the LSB 3. Two data bytes with D15 being the MSB and D0 being the LSB. It should be noted that each time a new destination register address needs to be written, the device address must be sent again. 8.6.5 DATA READ MODE
To read data from the device, a prepare read must first be done and then data read. The data read mode is explained in the signal diagram of Fig.6. Table 6 BYTE 1 2 3 4 Table 7 BYTE 1 2 3 4 5 6 L3 write data
FIRST IN TIME L3 MODE address data transfer data transfer data transfer L3 read data FIRST IN TIME L3 MODE address data transfer address data transfer data transfer data transfer ACTION ACTION
LATEST IN TIME
BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 device address register address data byte 1 data byte 2 0 0 D15 D7 1 A6 D14 D6 0 A5 D13 D5 1 A4 D12 D4 1 A3 D11 D3 0 A2 D10 D2 0 A1 D9 D1 0 A0 D8 D0
LATEST IN TIME
BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 device address register address device address register address data byte 1 data byte 2 0 1 1 0 or 1 D15 D7 1 A6 1 A6 D14 D6 0 A5 0 A5 D13 D5 1 A4 1 A4 D12 D4 1 A3 1 A3 D11 D3 0 A2 0 A2 D10 D2 0 A1 0 A1 D9 D1 0 A0 0 A0 D8 D0
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Philips Semiconductors
Preliminary specification
96 kHz IEC 958 audio DAC
8.6.6
INITIALIZATION STRING
UDA1351TS
For proper and reliable operation, the UDA1351TS must be initialized in the L3 control mode. This is required to have the PLL start up after powering up of the device under all conditions. The initialization string is given in Table 8. Table 8 BYTE 1 2 3 4 5 6 7 8 L3 initialization string and set defaults after power-up. FIRST IN TIME L3 MODE address data transfer data transfer data transfer address data transfer data transfer data transfer init string ACTION BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 device address register address data byte 1 data byte 2 set defaults device address register address data byte 1 data byte 2 0 0 0 0 0 0 0 0 1 1 0 0 1 1 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 0 1 0 0 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 0 LATEST IN TIME
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96 kHz IEC 958 audio DAC
UDA1351TS register map BIT FUNCTION D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Writable settings 00H system parameters default 10H sound features default 11H volume control DAC default 40H multiplex parameters default restore L3 defaults 0(1) 0(1) 0(1) 0(1) PON 1 M1 0 M0 0 BB3 0 0(1) BB2 0 0(1) BB1 0 BB0 0 VC5 0 1(2) 0(1) TR1 0 VC4 0 0(1) TR0 0 VC3 0 DE1 0 VC2 0 DE0 0 VC1 0 Auto MT 1 MT 1 VC0 0 RST PLL 0
Readable settings interpolator parameters SPDIF input and lock parameters PLL lock SPD lock ASF1 ASF0 PCM stat PRE MT stat ACC1 ACC0
UDA1351TS
Philips Semiconductors
Preliminary specification
96 kHz IEC 958 audio DAC
8.6.8 WRITABLE REGISTERS
UDA1351TS
-3 dB point for maximum setting is 300 Hz. The default value is `0000'. Table 13 Bass boost settings LEVEL (dB) BB3 0 0 0 0 0 0 0 0 1 1 1 1 1 BB2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 BB1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 BB0 FLAT 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MIN. 0 2 4 6 8 10 12 14 16 18 18 18 18 18 18 18 MAX. 0 2 4 6 8 10 12 14 16 18 20 22 24 24 24 24
8.6.8.1
Restoring L3 defaults
By writing to the 7FH register, all L3 control values are restored to their default values. Only the L3 interface is affected: the system will not be reset. Consequently, readable registers that are not reset can be affected.
8.6.8.2
Power-on
A 1-bit value to switch the DAC on and off. Table 10 Power-on setting PON 0 1 FUNCTION power-down power-on (default setting)
8.6.8.3
Filter mode selection
A 2-bit value to program the mode for the sound processing filters of bass boost and treble. Table 11 Filter mode settings M1 0 0 1 1 M0 0 1 0 1 maximum minimum FUNCTION flat (default setting)
1 1 1
8.6.8.6
De-emphasis
A 2-bit value to enable the digital de-emphasis filter.
8.6.8.4
Treble
Table 14 De-emphasis selection DE1 0 0 1 LEVEL (dB) 1 MAX. 0 2 4 6 Table 15 Soft mute selection MT 0 no muting muting (default setting) 1 FUNCTION DE0 0 1 0 1 fs = 32.0 kHz fs = 44.1 kHz fs = 48.0 kHz FUNCTION other (default setting)
A 2-bit value to program the treble setting, in combination with the filter mode settings. At fs = 44.1 kHz, the -3 dB point for minimum setting is 3.0 kHz and the -3 dB point for maximum setting is 1.5 kHz. The default value is `00'. Table 12 Treble settings TR1 0 0 1 1 TR0 FLAT 0 1 0 1 0 0 0 0 MIN. 0 2 4 6
8.6.8.7
Soft mute
A 1-bit value to enable the digital mute.
8.6.8.5
Bass boost
A 4-bit value to program the bass boost setting, in combination with the filter mode settings. At fs = 44.1 kHz, the -3 dB point for minimum setting is 250 Hz and the 2000 Mar 28 17
Philips Semiconductors
Preliminary specification
96 kHz IEC 958 audio DAC
8.6.8.8 Volume control 8.6.8.10 PLL reset
UDA1351TS
A 6-bit value to program the left and right channel volume attenuation. The range is from 0 to - dB in steps of 1 dB. Table 16 Volume settings VC5 0 0 0 0 : 1 1 1 1 1 1 1 1 1 1 1 1 1 VC4 0 0 0 0 : 1 1 1 1 1 1 1 1 1 1 1 1 1 VC3 0 0 0 0 : 0 0 0 0 0 1 1 1 1 1 1 1 1 VC2 0 0 0 0 : 0 1 1 1 1 0 0 0 0 1 1 1 1 VC1 0 0 1 1 : 1 0 0 1 1 0 0 1 1 0 0 1 1 VC0 0 1 0 1 : 1 0 1 0 1 0 1 0 1 0 1 0 1 -60 - -57 VOLUME (dB) 0 0 -1 -2 : -51 -52 -54
A 1-bit value to reset the PLL. This is the bit which is set in the initialization string. When this bit is asserted, the PLL will be reset and the output clock of the PLL will be forced to its lowest value, which is in the area of a few MHz. Table 18 PLL reset RST PLL 0 1 8.6.9 PLL is reset READABLE REGISTERS FUNCTION normal operation (default)
8.6.9.1
Mute status
A 1-bit value indicating whether the interpolator is muting or not muting. Table 19 Interpolator mute status MT stat 0 1 no muting muting FUNCTION
8.6.9.2
PLL lock detection
A 1-bit value indicating that the clock regeneration is locked. Table 20 PLL lock indication
8.6.8.9
Auto mute
PLL lock 0 1 out-of-lock locked
FUNCTION
A 1-bit value to activate mute during out-of-lock. In normal operation, the output is automatically hard muted when an out-of-lock situation is detected. Setting this bit to logic 0 will disable that function. Table 17 Auto mute setting Auto MT 0 1 FUNCTION do not mute output during out-of-lock mute output during out-of-lock (default setting)
8.6.9.3
SPDIF lock detection
A 1-bit value indicating the IEC 958 decoder is locked and is decoding correct data. Table 21 SPDIF lock detection SPD lock 0 1 FUNCTION not locked or non-PCM data detected locked and PCM data detected
2000 Mar 28
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Philips Semiconductors
Preliminary specification
96 kHz IEC 958 audio DAC
8.6.9.4 Audio sample frequency detection 8.6.9.6 Pre-emphasis detection
UDA1351TS
A 2-bit value indicating the audio sample frequency of the IEC 958 input signal. Table 22 Audio sample frequency detection ASF1 0 0 1 1 ASF0 0 1 0 1 44.1 kHz undefined 48.0 kHz 32.0 kHz FUNCTION
A 1-bit value that indicates whether the pre-emphasis bit was set on the IEC 958 input signal or not set. Table 24 Pre-emphasis detection PRE 0 1 FUNCTION no pre-emphasis pre-emphasis
8.6.9.7
Clock accuracy detection
8.6.9.5
PCM detection
A 1-bit value which indicates whether the IEC 958 input contains PCM audio data or other binary data. Table 23 Two channel PCM input detection PCM stat 0 1 FUNCTION input with two channel PCM data input without two channel PCM data
A 2-bit value indicating whether the timing accuracy of the IEC 958 input signal conforms to the IEC 958 specification. Table 25 Input signal accuracy detection ACC1 0 0 1 1 ACC0 0 1 0 1 level II level I level III undefined FUNCTION
9 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134). SYMBOL VDD Txtal Tstg Tamb Ves Ilu(prot) Isc(DAC) PARAMETER supply voltage crystal temperature storage temperature ambient temperature electrostatic handling voltage latch-up protection current short-circuit current of DAC Human Body Model (HBM); note 2 Machine Model (MM); note 3 Tamb = 125 C; VDD = 3.6 V Tamb = 0 C; VDD = 3 V; note 4 output short circuited to VSSA(DAC) output short circuited to VDDA(DAC) Notes 1. All VDD and VSS connections must be made to the same power supply. 2. JEDEC class 2 compliant. 3. JEDEC class B compliant, except pin VSSA(PLL), which can withstand ESD pulses of -130 to +130 V. 4. DAC operation after short circuiting cannot be warranted. - - 482 346 mA mA note 1 CONDITIONS MIN. 2.7 -25 -65 -40 -200 - MAX. 5.0 +150 +125 +85 +200 200 UNIT V C C C V mA
-2000 +2000 V
2000 Mar 28
19
Philips Semiconductors
Preliminary specification
96 kHz IEC 958 audio DAC
10 THERMAL CHARACTERISTICS SYMBOL Rth(j-a) PARAMETER thermal resistance from junction to ambient CONDITIONS in free air
UDA1351TS
VALUE 85
UNIT K/W
11 CHARACTERISTICS VDDD = VDDA = 3.0 V; IEC 958 input with fs = 48.0 kHz; Tamb = 25 C; RL = 5 k; all voltages measured with respect to ground; unless otherwise specified. SYMBOL Supplies; note 1 VDDA VDDA(DAC) VDDA(PLL) VDDD VDDD(C) IDDA(DAC) IDDA(PLL) IDDD(C) IDDD P analog supply voltage analog supply voltage for DAC analog supply voltage for PLL digital supply voltage digital supply voltage for core analog supply current of DAC analog supply current of PLL digital supply current of core digital supply current power consumption at 48 kHz power consumption at 96 kHz Digital input pins VIH VIL Vhys(RESET) ILI Ci Rpu(int) Rpd(int) VOH VOL IL(max) HIGH-level input voltage LOW-level input voltage hysteresis voltage on pin RESET input leakage current input capacitance internal pull-up resistance internal pull-down resistance IOH = -2 mA IOL = 2 mA 0.8VDD -0.5 - - - 16 16 - - 0.8 - - 33 33 - - 3 VDD + 0.5 V +0.2VDD - 10 10 78 78 - 0.4 - V V A pF k k power-on power-down at 48 kHz at 96 kHz at 48 kHz at 96 kHz at 48 kHz at 96 kHz DAC in playback mode DAC in Power-down mode DAC in playback mode DAC in Power-down mode 2.7 2.7 2.7 2.7 2.7 - - - - - - - - - - - - 3.0 3.0 3.0 3.0 3.0 8.0 750 0.7 1.0 16.0 24.5 2.0 3.0 80 58 109 87 3.6 3.6 3.6 3.6 3.6 - - - - - - - - - - - - V V V V V mA A mA mA mA mA mA mA mW mW mW mW PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Digital output pins HIGH-level output voltage LOW-level output voltage maximum load current 0.85VDD - - V V mA
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Philips Semiconductors
Preliminary specification
96 kHz IEC 958 audio DAC
UDA1351TS
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Digital-to-analog converter; note 2 Vref Vo(rms) reference voltage output voltage (RMS value) fi = 1.0 kHz tone at 48 kHz at 0 dB at -40 dB; A-weighted fi = 1.0 kHz tone at 96 kHz at 0 dB at -40 dB; A-weighted S/N signal-to-noise ratio at 48 kHz signal-to-noise ratio at 96 kHz cs Vo IEC 958 input Vi(p-p) Ri Vhys Notes 1. All supply pins VDD and VSS must be connected to the same external power supply unit. 2. When the DAC must drive a higher capacitive load (above 50 pF), a series resistor of 100 must be used to prevent oscillations in the output stage of the operational amplifier. AC input voltage (peak-to-peak value) input resistance hysteresis voltage 0.2 - - 0.5 6 40 3.3 - - V k mV channel separation unbalance of output voltages - - -85 -57 100 100 96 0.1 -80 -52 - - - 0.4 dB dB dB dB dB dB - - -90 -60 -85 -55 dB dB measured with respect to VSSA 0.45VDDA 0.50VDDA 0.55VDDA V - 900 - mV
(THD + N)/S total harmonic distortion-plus-noise to signal ratio
fi = 1.0 kHz tone; code = 0; 95 A-weighted fi = 1.0 kHz tone; code = 0; 95 A-weighted fi = 1.0 kHz tone fi = 1.0 kHz tone - -
2000 Mar 28
21
Philips Semiconductors
Preliminary specification
96 kHz IEC 958 audio DAC
UDA1351TS
12 TIMING CHARACTERISTICS VDDD = VDDA = 2.7 to 3.6 V; Tamb = -40 to +85 C; RL = 5 k; all voltages measured with respect to ground; unless otherwise specified. SYMBOL Device reset trst PLL lock time tlock time to lock fs = 32.0 kHz fs = 44.1 kHz fs = 48.0 kHz fs = 48.0 kHz Microcontroller L3 interface timing (see Figs 7 and 8) Tcy(CLK)(L3) tCLK(L3)H tCLK(L3)L tsu(L3)A th(L3)A tsu(L3)D th(L3)D t(stp)(L3) tsu(L3)DA th(L3)DA tsu(L3)R th(L3)R L3CLOCK cycle time L3CLOCK HIGH time L3CLOCK LOW time L3MODE set-up time for address mode L3MODE hold time for address mode L3MODE set-up time for data transfer mode L3MODE hold time for data transfer mode L3MODE stop time in data transfer mode L3DATA set-up time in address and data transfer mode L3DATA hold time in address and data transfer mode L3DATA set-up time in data transfer mode L3DATA hold time in data transfer mode read mode read mode 500 250 250 190 190 190 190 190 190 30 50 360 - - - - - - - - - - - - ns ns ns ns ns ns ns ns ns ns - - - - - - 85.0 63.0 60.0 40.0 ms ms ms ms reset active time - 250 s PARAMETER CONDITIONS MIN. TYP. UNIT
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Philips Semiconductors
Preliminary specification
96 kHz IEC 958 audio DAC
UDA1351TS
handbook, full pagewidth
L3MODE th(L3)A tCLK(L3)L tsu(L3)A L3CLOCK tCLK(L3)H th(L3)A tsu(L3)A
Tcy(CLK)(L3) tsu(L3)DA th(L3)DA
L3DATA
BIT 0
BIT 7
MGL723
Fig.7 Timing for address mode.
handbook, full pagewidth
tstp(L3)
tstp(L3)
L3MODE tCLK(L3)L tsu(L3)D tCLK(L3)H Tcy(CLK)L3 th(L3)D
L3CLOCK
th(L3)DA L3DATA write
tsu(L3)DA
th(L3)DA
BIT 0
BIT 7
L3DATA read ten(L3)DA th(L3)R tsu(L3)R tdis(L3)DA
MGL889
Fig.8 Timing for data transfer mode.
2000 Mar 28
23
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andbook, full pagewidth
X1
X1
X1
X1
X1
X1
VDDA(DAC) X1
VDDA L27 VDDD(C) BZN32A07 C11 100 F (16 V) C41 100 nF (50 V)
X1 X1 X1
VDDA VSSA VDDD(C)
23 22 21 6
24
4
18
28
25
14
VSSA(DAC) X1
VDDA(PLL)
VSSA(PLL)
TEST1
TEST2
TEST3
TEST4
VDDD
VSSD
LOCK
X1
X1
X1
2000 Mar 28
L3-bus
13 APPLICATION INFORMATION
Philips Semiconductors
96 kHz IEC 958 audio DAC
L26 VDDA BZN32A07 C12 100 F (16 V) C42 100 nF (50 V)
L29 VDDD C43 100 nF (50 V) C14 100 F (16 V) BZN32A07 VDDA
20 19
Vref
X1 C44 100 nF (50 V) C13 10 F (16 V)
5 X1 X1 X1 L3CLOCK L3MODE L3DATA
RESET
X1
C40 VDDD(C) 100 nF (50 V)
9 10 8 1 11 MUTE n.c. n.c. X1 X1 X1
VDDD(C)
3 2 1
J26 mute no mute
J14 3 static 2 1 L3 X16 IEC channel X11 R41 75
VDDD(C) C45 C48 180 pF (50 V) 10 nF (50 V)
X1
SELSTATIC
26
UDA1351TS
2 12 27
24
ground +3 V C3 100 F (16 V)
X1
SPDIF
VSSD(C) X1 n.c. X1
13
15
VOUTL
X1
C15 47 F (16 V)
R44 100 R43 10 k
X18 output left X13
AGND
DGND J1 J3 J2 C5 100 F (16 V) 3 VDDA VDDD(C) VDDD R38 1 C9 100 F (16 V) C28 100 nF (50 V) lock R39 1 k V5 7 16
17
MGU035
VOUTR X1
C16 47 F (16 V)
R46 100 R45 10 k
X19 output right X14
Preliminary specification
UDA1351TS
VDDD
AGND DGND
Fig.9 Test and application diagram.
Philips Semiconductors
Preliminary specification
96 kHz IEC 958 audio DAC
14 PACKAGE OUTLINE SSOP28: plastic shrink small outline package; 28 leads; body width 5.3 mm
UDA1351TS
SOT341-1
D
E
A X
c y HE vMA
Z 28 15
Q A2 pin 1 index A1 (A 3) Lp L 1 e bp 14 wM detail X A
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 2.0 A1 0.21 0.05 A2 1.80 1.65 A3 0.25 bp 0.38 0.25 c 0.20 0.09 D (1) 10.4 10.0 E (1) 5.4 5.2 e 0.65 HE 7.9 7.6 L 1.25 Lp 1.03 0.63 Q 0.9 0.7 v 0.2 w 0.13 y 0.1 Z (1) 1.1 0.7 8 0o
o
Note 1. Plastic or metal protrusions of 0.20 mm maximum per side are not included. OUTLINE VERSION SOT341-1 REFERENCES IEC JEDEC MO-150 EIAJ EUROPEAN PROJECTION
ISSUE DATE 95-02-04 99-12-27
2000 Mar 28
25
Philips Semiconductors
Preliminary specification
96 kHz IEC 958 audio DAC
15 SOLDERING 15.1 Introduction to soldering surface mount packages
UDA1351TS
If wave soldering is used the following conditions must be observed for optimal results: * Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. * For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 15.4 Manual soldering
This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering is not always suitable for surface mount ICs, or for printed-circuit boards with high population densities. In these situations reflow soldering is often used. 15.2 Reflow soldering
Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 C. The top-surface temperature of the packages should preferable be kept below 230 C. 15.3 Wave soldering
Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed.
Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
2000 Mar 28
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Philips Semiconductors
Preliminary specification
96 kHz IEC 958 audio DAC
15.5 Suitability of surface mount IC packages for wave and reflow soldering methods
UDA1351TS
SOLDERING METHOD PACKAGE WAVE BGA, LFBGA, SQFP, TFBGA HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS PLCC(3), SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO Notes 1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods". 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. 16 DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. 17 LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications. not suitable not not not suitable(2) recommended(3)(4) recommended(5) suitable REFLOW(1) suitable suitable suitable suitable suitable
2000 Mar 28
27
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For all other countries apply to: Philips Semiconductors, International Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 2000
Internet: http://www.semiconductors.philips.com
SCA 69
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
753503/25/01/pp28
Date of release: 2000
Mar 28
Document order number:
9397 750 06814

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